Apparatuses and embodiments described herein relate to a semiconductor package having a hollow structure, and a method for manufacturing the same.
As a method for package of semiconductor devices, although mold-typed packages have been conventionally used, chip size packages (CSPs) have recently attracted attention according to requirements for reduction of package size from markets. Among other things, when CSP is applied to a MEMS device requiring a hollow structure on a surface of a functional device represented by an optical device, a method of bonding a device substrate to a protection substrate made of glass or the like via a junction layer having a hollow pattern formed thereon is used. After bonding the protection substrate, the hollow pattern becomes a hollow structure.
Since there is a need to form a hollow structure on a photosensitive portion in an optical device, the hollow pattern is formed on the junction layer in such a manner that the hollow pattern exposes the photosensitive portion. In other MEMS devices, a hollow pattern is formed on a sensing portion and an operating portion. The material of the junction layer may be optional without being limited to organic material and inorganic material. In particular, in many cases, an optical device employs a junction layer made of resin from restrictions such as an upper limit of process temperature due to heat resistance of a photosensitive portion made of resin.
In addition, a method of forming the hollow pattern may include a dispense method, a print method and so on, which are simple and inexpensive. However, a photolithography for photosensitive resin material is the mainstream in semiconductor industries which have made noticeable progress in miniaturization of device surface machining.
Acryl is representative of resin material to which photolithography can be applied and which has adhesive properties as a junction layer. In addition, even for a material having adhesiveness but no photosensitivity, by mixing a photosensitive ingredient in the material, it is possible to obtain a junction material to which photolithography can be applied. Many proposals have been made to use epoxy, silicon, phenol, polyimide or a mixture thereof as such a resin material.
Exhibition of adhesion of such a resin material requires a thermosetting reaction by thermocompression of the subject substrate and the resin material, which is performed after patterning the resin material. Main parameters for the thermocompression are an atmosphere pressure, a compression pressure, a compression temperature, etc. in bonding.
Two qualities are required after the hollow package is formed using the resin material. The first quality is package reliability (adhesion). In order to secure this quality, there is a need of thermocompression conditions to draw out an inherent adhesive strength of the junction layer material sufficiently. In addition, there is a need to prevent a loss of adhesion area caused by mixture of foams into an adhesive interface.
In order to draw out the inherent adhesive strength of the junction layer material sufficiently, there is a need to press the adhesive material against the subject substrate at an initial stage of adhesion such that the adhesive material approaches the subject substrate by a distance sufficient to exhibit chemical adhesion strength. As a process condition in doing so, there is a need to increase both a compression pressure and a compression temperature on the whole. In order to eliminate the mixture of foams into the adhesive interface, which has an effect on both reliability and appearance quality, there is a need to decrease an atmosphere pressure in boding as well as the high compression pressure and high compression temperature.
The second quality is a package appearance quality. Specifically, it is required that foams should not be mixed into the adhesive interface and a junction layer pattern after thermocompression should be little different in width from a junction layer pattern before thermocompression (that is, their dimension remains unchanged).
The main reason for dimension change is plastic deformation of the junction layer material in thermocompression and rheological deformation produced beyond a softening point. If the degree of deformation is too large, it has an effect on the appearance quality and also results in permeation of the junction layer material up to a surface of a photosensitive region in an optical sensor, thereby causing the characteristic failure of a device. Since a process condition where deformation is apt to occur is that both a compression pressure and a compression temperature are substantially high, a low compression pressure and a low compression temperature are required to suppress the deformation.
In this manner, since the reliability and the appearance quality of the hollow package are diametrically opposed in terms of the thermocompression conditions required to secure the reliability and the appearance quality, there is a need to adjust the thermocompression conditions for compatibility of the reliability with the appearance quality.
In view of such a compatibility problem, there has been proposed a structure where a bank is provided between a light receiving portion of a solid-state imaging device and an adhesive resin in order to prevent the adhesive resin from penetrating into the light receiving portion (refer to Patent Document 1 below). Although this proposal facilitates the adaptation of a process of high compression pressure and high compression temperature since the bank functions to prevent the adhesive resin from being introduced into the light receiving portion, this proposal does not disclose a solution related to maintenance of pattern dimension.
In the related art, one of the reasons for difficulty in compatibility of reliability with appearance quality may include a relationship between position and dimension of a hollow pattern of a device chip. FIG. 11 is a schematic plan view showing a conventional optical device chip. In this figure, reference numeral 101 denotes a photosensitive region, reference numeral 102 denotes a hollow region, reference numeral 103 denotes an adhesive region, reference numeral 104 denotes an optical device chip and reference numeral 112 denotes an electrode pad on the optical device chip. The electrode pad is provided to make an electrical connection of the optical device chip to an external circuit using fine metal lines, through wires or the like. Although not shown, fine surface wires are formed between the photosensitive region and the electrode pad in an actual optical device chip, and in addition, a plurality of functional elements is interposed between the wires.
In FIG. 11, the aspect ratio of the photosensitive region is different from that of the device chip but has the same center coordinate as the device chip. In FIG. 11, Wh1, Wh2, Wv1 and Wv2 denote widths of the adhesive region, that is, widths in the left, right, upper and lower sides, respectively, of the hollow region in FIG. 11.
The conventional mainstream design for a hollow package is to provide a hollow region distant by equal intervals from the photosensitive region. As shown in FIG. 11, if the design is made as conventional when the photosensitive region is different in aspect ratio from the device chip, a difference occurs between four sides of the adhesive region. In FIG. 11, Wh1=Wh2<Wv1=Wv2.
FIG. 12 illustrates a distribution of stress applied to an junction layer, which is drawn according to finite element analysis, when a subject substrate having the same size as the device chip is pressed against the device chip where Wh1=Wh2<Wv1=Wv2 as in FIG. 11. A level bar provided in the lower side of FIG. 12 indicates a “stress value” meaning that stress increases from the left side (indicated in blue color in original figure) to the right side (indicated in red color in original figure).
In FIG. 12, it is apparent that more stress is applied to the narrower horizontal adhesion width (Wh1 and Wh2) than the wider vertical adhesion width (Wv1 and Wv2). In other words, when the subject substrate is pressed with a certain load against the entire surface of the junction layer having the different size, nonuniformity of local stress occurs due to differences in their widths. As a result, plastic deformation of junction material is likely to occur due to overstress in the region having narrower adhesion width, while junction failure such as a foam mixture is likely to occur due to low stress in the region having wider adhesion width.
FIG. 13 is a schematic plan view of another optical device chip. FIG. 13 is characterized in that the photosensitive region is different in aspect ratio and center coordinate from the device chip. Accordingly, the relationship between their adhesion widths is Wh1≠Wh2≠Wv1≠Wv2. Since an actual device chip is designed in consideration of arrangement of structures other than the photosensitive region, it is common that the center coordinate of the photosensitive region is deviated from that of the device chip, as shown in FIG. 13. When a hollow region for such a device chip is formed distant by a distance of equal intervals from the photosensitive region, as conventional, it can be envisaged that a distribution of stress in thermal pressing is more deteriorated than in the case shown in FIG. 12 (that is, more significant nonuniform local stress is produced).    [Patent Document 1] Japanese Unexamined Patent Application, First Publication No. 2003-92394
In consideration of the above circumstances, it is an aspect of exemplary embodiments of the present invention to provide a semiconductor package with a hollow structure, which makes junction reliability compatible with dimension maintenance by uniformizing an in-plane stress applied when a semiconductor substrate is bonded to a protection substrate by thermocompression.
It is another aspect of exemplary embodiments of the present invention to provide a method of manufacturing a semiconductor package with a hollow structure, which is capable of uniformizing an in-plane stress applied when a semiconductor substrate is bonded to a protection substrate by thermocompression, thereby easily obtaining a semiconductor package with compatibility of junction reliability with dimension maintenance.